FICS Research - OPS

 

FICS Research is looking for students with knowledge and/or experience in the following to fill several part-time, OPS positions:

VHDL/Verilog (Hardware Description Language); IP XACT, SOC Design, Bus standards

 15-20 hours per week at $15 per hour

Please send CV/resume and a few sentences about your experience to lesly@ufl.edu.