At Florida Institute for Cybersecurity (FICS) Research, we have some open OPS positions focusing on different aspects of SoC designs. Preferred candidates should be from ECE/CISE background or be pursuing an MSc in Computer Engineering program and have strong expertise in Verilog/VHDL and CAD tools, simulation and verification. Prior experience in RTL development is a plus.
Part-time, 20 grs a week, at a rate of pay of $15 pr hour.Interested candidates please contact at fahimrahman@ece.ufl.edu.
